The present invention concerns data communications between electronic devices or circuits, particularly programmable phase-locked loops suitable for use in high-speed receivers, transmitters, and transceivers.
In the computer and telecommunications industries, many electronic devices are typically coupled together to operate as systems. In such systems, a common occurrence is the communication of data between two devices: a sending device and a receiving device.
The sending device generally has the data in the initial form of a set of digital words (sets of ones and zeros). In the sending device, a transmitter circuit converts each word into a sequence of electrical pulses, with each pulse timed according to a data clock, and transmits the timed sequence of pulses through a cable, circuit board, or other medium to the receiving device. The receiving device includes a receiver circuit that first determines the timing of the pulses and then identifies each of the pulses in the signal as a one or zero, enabling it to reconstruct the original digital words.
A key component in both the transmitter and the receiver is a voltage-controlled oscillatorxe2x80x94a circuit that outputs a signal that varies back and forth between two voltage levels at a frequency based on an input control voltage. In the transmitter, a voltage-controlled oscillator controls timing of the pulses output by the transmitter, and in the receiver, it facilitates reconstruction of the digital words from the transmitted pulses.
Although there are several types of voltage-controlled oscillators, one type often used in serial data transmitters and receivers is the ring oscillator. Conventionally, the ring oscillator comprises a chain of delay circuits arranged in a straight line. Each delay circuit has an input coupled to an output of the preceding delay circuit, with the output of the last delay circuit in the line coupled to the input of the first delay circuit in the line to form a loop, or ring. All the delay circuits are coupled to a common control voltage which controls how much delay is applied to signals passing through them.
One problem the present inventors recognized with this conventional straight-line arrangement for ring oscillators is that the signal-path length (that is the length of the conductive path for a signal to travel) from the output of one delay circuit to the input of the next delay circuit, can vary significantly depending on the particular pair of delay circuits. For example, in a ten-circuit line, the signal path from the first delay circuit to the second delay circuit is roughly ten times shorter than the signal path from the tenth delay circuit in the line back to the first delay circuit. Thus, the effective delay of the tenth delay circuit is longer than that of the first delay circuit.
Although signal-path differences can be largely ignored for lower-frequency communications, they cannot at higher frequencies because the margin for timing error is much stricter. At higher data frequencies, the inconsistent delays stemming from signal-path differences undermine the ability of receiver circuits to reliably recover digital data from transmitted signals.
Accordingly, there is a need for ring oscillators that have better matched signal-path lengths.
To address these and other needs, the present inventors devised several unique ring- oscillator layouts that provide improved matching of signal-path lengths. A first exemplary oscillator includes a group of at least four delay circuits arranged in a sequence, with each delay circuit having at least one adjacent delay circuit in the sequence and at least one non-adjacent delay circuit in the sequence. The exemplary oscillator further includes at least two input-output connections between non-adjacent delay circuits. In contrast, conventional ring oscillators have only one input-output connection between non-adjacent delay circuitsxe2x80x94the connection between the first and the last delay circuits. The additional non-adjacent input-output connections tend to equalize or reduce the signal-path differences between the delay circuits, thereby improving oscillator performance, particularly at higher frequencies of oscillation.
A second exemplary ring oscillator includes a group of at least three delay circuits arranged to define a closed loop. Specifically, this exemplary embodiment includes a non-collinear (non-straight-line) arrangement of at least a first, a second, and a third delay circuit, with each having respective inputs and outputs. The output of the first is coupled to the input of the second; the output of the second is coupled to the input of the third; and the output of the third is coupled to the input of the first.
A third exemplary ring oscillator includes at least two groups of sequentially arranged delay circuits and a bus positioned between them. The bus includes one line for each of the delay circuits in the two groups, with each line coupled to an input of one of the delay circuits and an output of another delay circuit.
Other aspects of the invention include a phase-locked loop, receiver, transmitter, and transceiver that incorporate the exemplary ring oscillators. Still other aspects of the invention combine one or more of these components with programmable logic devices to define a system.